An arithmetic processing device such as a central processing unit (CPU) includes a cache memory for holding a portion of data stored in a main storage device, an executing section for executing an instruction, and a controller for controlling the executing section and the like. The executing section has a first register file for holding a portion of the data held in the cache memory, a second register file for holding a portion of the data held in the first register file, and a computing section for executing computation based on an instruction, for example. The computing section executes the computation using data transferred from the second register file.
An error may occur in data held in a register file such as the first register file. Thus, an arithmetic processing device, which causes the register file to hold data having, added thereto, parity data for error detection and error checking and correction (ECC) data for error correction, has been proposed (refer to, for example, Domestic Re-publication of PCT International Publication Pamphlet No. WO2008/152728). An arithmetic processing device of this type includes an error detector for detecting the occurrence of an error and an error corrector for correcting the error.
In a pipeline process of executing each instruction at multiple stages, the result of computing a first instruction may be written back to a register (for example, a register included in the first register file) holding input data to be used for computation of a second instruction succeeding the first instruction. In this case, in an arithmetic processing device that executes a process of determining an error upon the transfer of data from the second register file to a computing section, it may be difficult to correct data including the error and re-execute the instructions. For example, if a commit for completing the first instruction is not stopped in time, a computed result obtained based on the commit for the first instruction is written to the register holding the input data (data including the error) to be used for the second instruction and it is difficult to correct the error in the input data and re-execute the second instruction.
In addition, if the first instruction is a multi-flow instruction obtained by dividing a single instruction into multiple flows, and a commit for the first flow of the first instruction is not stopped in time, it is difficult to correct the error in the input data and re-execute the second instruction. For example, if the first instruction is not re-executed due to the termination of a commit for the second and later flows of the first instruction, the second instruction that succeeds the first instruction is not re-executed.
In the state in which the instructions are not re-executed, functions of the computing section and the like are stopped and the performance of the arithmetic processing device is reduced, compared with a case where the instructions are re-executed.
According to an aspect, an arithmetic processing device and a method of controlling the arithmetic processing device that are disclosed herein aim to suppress a reduction in the performance of the arithmetic processing device.